Method and system for finding or plotting an optimum path

ABSTRACT

Nodal and link elements are arranged to simulate a system between which a path is to be formed, the link element including, selectively, time delays in accordance with characteristics of the interconnections between nodal points of the system. A point, or set of points forms a departure point, and a single, or a set of points forms an arrival point. A signal applied (under control of a clock) to a node will propagate along the links from nodeto-node, in accordance with the timing of the delaying circuits on the links. Once a signal is applied to the node, the node is inhibited from accepting other signals, so that the shortest (smallest delay) path from a departure to an arrival point is established. A tracing signal is then propagated along a parallel path from the departure to the arrival point, so that the path can be displayed.

United States Patent Champeaux, France [21] Appl. No. 618,906 [22] FiledFeb. 27, 1967 [45] Patented [73] Assignee Jan. 26, 1971 Societe Anonyme:Societe Nationale dEtude et de Construction de Moteurs dAviationS.N.E.C.M.A.

Paris, France [32] Priorit Feb. 26, 1966 [3 3] France [3 l 51,268

[54] METHOD AND SYSTEM FOR FINDING OR [56] References Cited UNITEDSTATES PATENTS 3,474,240 10/1969 Marquis et al. 235/ l 85 3,053,4539/1962 Bock et a1 235/185 3,250,902 5/1966 Mauchly 235/185 3,289,32312/1966 Fondahl 35/24 3,380,177 4/1968 Wagner 35/24 Primary Examiner-Malcolm A. Morrison Assistant Examiner- Felix D. Gruber Attorney stephenH. Frishauf I ABSTRACT: Nodal and link elements are arranged to simulatea system between which a path is to be formed, the link elementincluding, selectively, time delays in accordance with characteristicsof the interconnections between nodal points of the system. A point, orset of points forms a departure point, and a single, or a set of pointsforms an arrival point. A signal applied (under control of a clock) to anode will propagate along the links from node-to-node, in accordancewith the timing of the delaying circuits on the links. Once a signal isapplied to the node, the node is inhibited from accepting other signals,so that the shortest (smallest delay) path from a departure to anarrival point is established. A tracing signal is then propagated alonga parallel path from the departure to the arrival point, so that thepath can be displayed.

PATENTEDJmzsiQfl sum a nr '4 FROM CLOCK l TERM. ls,

COUNTER Fig.

METHOD AND SYSTEM FOR FINDING OR PLOTTING AN OPTIMUM PATH The presentinvention relates to apparatus to solve the problem of determining theoptimum path between states of a certain system. This system is entirelydefined by a predetermined number of variables (which may include time).For each state of the system, each of the variables takes apredetermined value and the state is defined by all said value s. Eachof these possible states can be represented in a geometrical spacehaving the same number of dimensions as the system includes variables. Astate is then defined by a point in this space.

The geometrical space in question is instrumented by devising ananalogue network. The points of the space will be represented by thenodes of the network, and the connections between these points will berepresented by connecting links forming the mesh of the network; in thedescribed embodiment of the network is electrical.

More precisely, two subsets are defined in a set of points, one of whichconstitutes a first family of points, known as departure points, and theother a second family of points, known as arrival points. As each of thepoints of the first family can be connected to each of the points of thesecond family by a large number of paths, it is a specific object of theinvention to determine the optimum path coupling a departure to a pointof arrival.

For certain applications, the family of departure points as well as thatof the arrival points can be reduced to one point only.

For other applications, a departure point may also function as anarrival point.

The problem as set out above is very general. By way of particularexamples, it may relate to urban traffic, the solution of problems ofdistribution of products or services, or the calculations of theshortest routes in transoceanic flights.

SUBJECT MATTER OF THE INVENTION An interconnected mesh network isprovided whose nodes correspond to points, all representative ofstatesof a system with a plurality of variables in a geometrical spacehaving the same number of dimensions as the system comprises variables,and whose mesh lines with different weightings, correspond to all theconceivable elementary passages between the different nodes. Accordingto the invention, a group of nodes representing a first family ofpoints, and another group of nodes representing a second family ofpoints, known as arrival points are selected and their addresses stored;during a first stage, emitted simultaneously from all the arrival nodesselected initially, signals progress along the lines of theinterconnecting mesh, leaving nodes and progressing towards theintermediate nodes which thus in turn become selected. The selection ofa node has the effect that during this stage the reception of othersignals at the selected node is inhibited. Additionally, thestep-by-step progression of the signals from the selected nodes isenabled and further, a connection through the interconnecting line overwhich the selection of the node occurred, is established. Fromintermediate nodes thus selected new signals are emitted as above, andso on. The interconnection line to the departure node over which one ofthese signals first reaches the departure node, is determined and theprogression of the signals is then stopped. In a second stage, aconnection is established from this departure node over the path thusdetermined, terminating at the arrival node from which the signaloriginated.

The invention also consists in a system for carrying out this method.

The essential characteristics of the method and of the system of theinvention will clearly appear from the following description, referringto the accompanying drawings in which:

FIG. 1 represents a network developed in a two-dimensional space andrepresentative of a particular problem to be solved,

FIG. 2 schematically shows an embodiment of the circuits enabling thenodes and the connecting links of the network of FIG. 1.

FIG. 3 represents an embodiment ofa nodal element" corresponding to anode ofthe network,

FIG. 4 represents an embodiment of a cone connecting link termed a loopclement,"

FIG. 5 represents an embodiment of an element for weighting theconnection links of the network, and

FIG. 6 represents a modification of the circuit displaying the optimumpath of the system according to the invention.

Referring now to the drawings, FIG. 1 shows a network in atwo-dimensional space.

In this network, the nodes N1 to N10 represent different statesconsidered in a given problem, whilst the interconnecting lines, alsocalled loops 1 to 13 constitute paths permitting passage of signals fromone node to another node, or progressible change of state in theproblem.

The connection lines are oriented and thus reproduce the sense of theconnections between the various states in the problem in question. InFIG. 1, all the loops are in one direction; however, they could also bein two directions by arranging two lines in parallel oriented inopposite direction.

For purposes of initial explanation, let N1 be the departure node and N2the arrival node.

At the side of each reference for the loops, a weighting applied to eachof the loops has been indicated in parentheses. Thus it is that theconnection 1 is not weighted and consequently has weighting ratio of 1.On the other hand, the connection 4 has a weighting ratio of 2,corresponding to two progression times of the step-by-step progressionover line 4 between N4 and N5, whilst the loop 9 has a weighting ratioof 3 corresponding to three progression times of the step-by-stepprogression over line 9 between N7 and N8.

FIG. 2 shows, in enlarged scale and greater detail, a departure node A,an arrival node B and an intermediate node M. The two elementary pathspermitting passage from the node A to node B are shown by the loops I4and 15.

The nodes A, B and M are represented respectively by nodal elements PA,PB and PM which are identical, whilst the loops I4 and 15 are shownrespectively by loop elements" V14 and V15 are also identical.

Each nodal element" comprises three outputs S1, S2 and S3 and threeinputs E1, E2 and E3. Each connection line (loop element) comprises twooutputs S4 and 55 connected respectively to the input E1 of the nodalelement end of the connection through an OR gate 17 and to the input E2of the nodal element" forming the origin for the signals in the linethrough an OR gate 16. Four additional inputs E4, E5, E6 and E7 areprovided.

The inputs E4 and E7 are respectively connected to the outputs S1 and S2of the sending (origin of signals) nodal element. The inputs E3 and E5are respectively connected to the outputs 20 and 18 of a clock 19. InputE6 is connected to the output S3 of the receiving nodal element.

In the case where any one of the nodes A, B and M are, additionally,connected to other connection lines (e.g. node N3, FIG. 1), the loopelements" corresponding to these additional connections are connected ina manner identical to the connection of loop element" V15 to the nodalelement PM. Thus, the supplementary terminals 21, 22 and 23 will beconnected respectively to the input E7, to the output S5 and to theinput E4 of each of the additional loop elements forming part of anotherconnection link, or loop from the same original nodal element"; in FIG.2, nodal element PA. Lines 21', 22', 23' may form an additionalconnection to nodal point PM.

Similarly, in the case where the nodes A, B and M are ends of otherlines (e.g. node N5, FIG. I), the lines 24, 24 to the gates 17 may forma second input connected to the output S4 of each of the additionalconnecting loop elements relatively to the same end nodal element.

FIG. 3 shows the circuit of a "nodal element." This nodal element iscomposed of a bistable memory whose output is connected to S3 and whoseinput is connected to an AND gate 26 comprising two inputs located at E2and at E3 and a noninverting amplifier 27 whose input is located at E1and its output at S1. In addition, the output of the memory 25 includesa shunt located at S2.

FIG. 4 shows the circuit of a connection link, or loop element." Thisloop element" comprises a bistable memory 28 whose output is located atSS and whose input is connected to an AND gate 29 with five inputs, twoof which are located at E5 and E6; an inverting amplifier 30 whose inputis located at E7 and whose output is connected to one of the inputs ofthe AND gate 29; a noninverting amplifier 31 whose input 32 isconnected, if desired, to a weighting element and whose out put isconnected to one of the inputs of the AND gate 29; a second noninvcrtingamplifier 33 whose input is located at 34 and whose output is connectedto one of the inputs of the AND gate 29; and an AND gate 35 whose outputis located at $4 and whose three inputs are connected, one to the outputof the bistable memory 28, the other to the input E4 and the third to asupplementary input terminal 36 through a noninverting amplifier 37.

FIG. 5 shows the circuit of a weighting element intended to weight aconnecting link, or loop element." This weighting element essentiallycomprises a binary counter 38 whose input is connected to an AND gate 39whose two inputs, located at 40 and 41, can be connected on the one handto the output S3 of the nodal element" end of the loop element to beweighted and on the other hand to the terminal 18 of the clock 19,whilst the output of the binary counter 38 is connected to the n inputsof a decoding or coincidence gate 42 preset for a predetermined numberof counts, depending on the weighting factor, whose output 43 can beconnected to the input 32 of the loop element" to be weighted.

The operation of the above described system is as follows:

Let us firstly consider the circuit represented in FIG. 2 by the nodalelements PA, PB and PM and the loop elements" V14 and V15.

The path to be recognized is that permitting the passage from the nodeA, termed the departure (or origin) node, to the node B, termed thereceiving or arrival node. it passes through the intermediate orconnecting node M.

A node becomes the departure node A when a peripheral device (not shown)applies a continuous send" or departure" activation or addressing signalto the input terminal E1 of a nodal element"; in FIG. 2, nodal elementPA. A node becomes an arrival node B, when a a peripheral device (notshown) applies an appropriate continuous arrival activation signal tothe input tenninal E2 ofa nodal element"; in FIG. 2, nodal element PB.

During the whole time of operation, the clock 19 alternately andcontinuously supplies two signals T1 and T2. Signal T1 is applied to theoutput 20 and T2 to the output 18.

The initial state of the memory 25 (FIG. 3) of the nodal elements issuch that an inhibiting signal appears on the outputs S2 and S3 of thesenodal elements before these memories are triggered (so that bistablememory 25 will change state). The initial state of the memory 28 of theloop elements" (FIG. 4) is such that an inhibiting signal appears on theoutput S5 of these loop elements before these memories are triggered tochange state.

During the operation, the nodal element PB recognizes the appearance ofthe first signal T1 from clock 19, on line 20, connected to terminal E3(FIG. 3). AND gate 26 (FIG. 3) is now activated (T1 on E3, and E2 by thearrival activation signal from the peripheral device). This nodalelement is the only one in the mesh network which has its memorytriggered, since the inputs E2 of the other nodal elements do notreceive an activating signal.

At the moment, the memory 25 of the nodal element PB triggers, theoutput S3 of this element activates one of the inputs of the AND gate 29of the loop element" V15, through the input E6 (FIG. 4).

Upon the following signal T2. in the absence of inhibition applied tothe AND gate 29 through the lack of input 34, the AND gate 29 has allits inputs active.

It has been assumed in this example that the loop elements" do notcomprise weighting elements and that consequently no inhibition isapplied through the input 32 to the AND gate 29. AND gate 29 also has anactive input at E7 since the "nodal element" PM, the origin of the loopele ment" V15 does not yet store any signal. Memory 25 of element PM hasnot yet been triggered, and the output S2 ofthis nodal element" deliversan inhibit signal which, inverted by the inverter 30 of the loopelement" V15. permits activation ofAND gate 29.

The first clock signal T2 (subsequent to clock Tl) thus causes storageof a condition in the "loop element" V15. Additionally, change of stateof element 28 activates one of the inputs of the AND gate 35 and also,by means ofthe output S5 over OR gate 16, input E2 of the AND gate 26 ofthe nodal element" PM.

The second signal T1 completes the activation of AND gate 26 of the"nodal element" PM; this "nodal element is for its turn memorized (thatis, stores a condition) and activates, upon change of state of itselement 25, through its output S3, the input E6 of the AND gate 29 ofthe "loop element V14.

The series of operations for passing from the node M to node A isrepeated in the same manner as during the passage from node B to node M.Thus it is that the next (second) signal T2 will activate the loopelement" V14; the third T1 signal finally activates one of the inputs ofits gate 35 and, through its output S5 and the input E2 of the nodalelement-- PA one of the inputs of the gate 26 of this element.

At the moment when the memory 28 of a loop element" connected to thedeparture" node B has been triggered, the send" or departure" activationsignal has been applied to the input E1 of the nodal element PA by theperipheral device, as referred to above.

This signal is present at the output 51 of the nodal element PA andactivates input E4 of the AND gate 35 of the loop element V14. Gate 35is entirely activated if no nonvalidating signal (which is normally thecase) is applied through the input 36 and memory 28 has triggered. Theuse of signals to terminals 36, 32 and 34 will be described below. Thesend" signal passes through the AND gate 35, is present at the output S4of the loop element V14, passes through OR gate 17, terminals E1,amplifier 27 and terminal S1 ofnodal element PM, passes through the loopelement" V15 and the nodal element PB in order to appear at the outputS1 thereof. 7

The setup of a continuous circuit path running from A to B is thuseffected by guiding the starting send signal through the outputs S1 ofthe nodal elements" PA, PM and PB, and the outputs S4 of the "loopelements" V14 and V15.

The device to be described plots in a single operation, for the purposeof exploration, the desired passage between the point of departure andpoint of arrival. For certain uses it may be useful or necessary thatthis passage appears step-by-step either at a given rhythm, or in replyto successive orders sent to said device.

This modification is obtained by replacing the amplifier 27 in the nodalelement" (FIG. 3) by a master-slave circuit, or by a circuit as shown inFIG. 6. Instead of amplifier 27, a first logic AND gate 50 having twoinputs 51 and 52 controls a first bistable circuit 53; the output ofthis first bistable circuit 53 feeds an input 54 of a second AND gate56. The output of AND gate 56 is connected to a second bistable circuit57 whose output constitutes the output S of the nodal element."

The operation of this circuit is such that the signal intended to markthe different stages of the path can progress only from one nodalelement" to the following nodal element" during a cycle of signals Uconnected to input 52 of AND gate 50 and U connected to input 55 of ANDgate 56, which are exclusive of one another and which control thepropagation of a signal in this circuit.

When it is a question of circuits known as master-slave," the cycle ofsignals if formed by the succession of the two voltage levels which canbe applied to the corresponding input of these well known circuits. Whenit is a question of the present circuit with double bistable circuits,the progression of the display signal is obtained by applying a firstsignal U1 to the input 52 of the first AND gate 50, this causing theinput signal present on the input E1 of the nodal element to progressand to be memorized in the bistable circuit 53. This signal cannot goany further if, the second signal U2 is absent. When it is desired tocause the signal to progress, the first signal U1 is terminated and thesecond signal U2 is applied to the input 55 of the AND gate 56. Theother input 54 of this gate being activated by the triggered bistablecircuit 53, bistable circuit 57 triggers in turn. Thus, the signalappears at the outputs S1 of the nodal element and after having cleareda loop element," appears at the input E1 of the following nodalelement." There it is stopped by the AND gate 50 of this nodal element,"which is not activated in the absence of a signal U1. The progression ofthe display signal will thus be effected at the rhythm of the signalsU1, U2. The setup of the path is backwards, but the signal which mustpass through the path leaves from the point of origin to the end pointso that the path is defined in correct order. One of the bistablecircuits of each nodal element" can be used for making the path.According to whether the bistable circuits will be returned to zero, orif they remain triggered, the path can be indicated step-by-step or anyprevious steps may be indicated. If with an arrangement of FIG. 6, it isdesired to have the path established in a single step, it is onlynecessary to apply the signals U1 and U2 simultaneously. This is notpossible with the master-slave circuit.

Reference will now again be made to FIG. 1. Let N1 be the departurenode, and the node N6 the arrival node. The problem to be solved is thedetermination of the shortest path between nodes N l and N6. Contrary tothe arrangement in the preceding example, the loop elements" here areweighted, according to a ratio indicated in parentheses, as follows:

It has been seen in the preceding example that the storing of a path,which may be termed memorization of a loop element" is effected by asignal T2, that is by an activating signal delivered to the output 18 ofthe clock 19 when the nodal element" end of the loop element in questionhas been activated. In order to weight a loop element, it will thus besufficient to control the memorization of this element, no longer at thefirst signal delivered to the output 18 of the clock 19 and according tothe memorization of the nodal element" end of said loop element, but atthe second, the third, or the nth clock output at 18, according to theweighting ratio.

To this end, the binary counter 38 (FIG. 5) of a weighting elementassociated with the loop element to be weighted, counts, by means of theterminal 41 connected to the output 18 of the clock 19, the number ofsignals emitted on the output 18 of the clock 19. As long as the desirednumber of these signals is not reached, the weighting element maintainsthrough its output 43, connected to the input 32 of the loop element,"an inhibiting signal on the AND gate 29.

When the number of the signals emitted by the output 18 of the clock 19,corresponding to the weighting of the loop element" in question,diminished by one, is reached, the weighting element lifts thisinhibition and the loop element" can be memorized at the followingsignal if no other inhibition appears before this instant.

In FIG. 1, the loops whose weighting ratio is 1 correspond to loopelements" comprising no weighting elements, whilst the loops 4 and 9correspond to loop elements" comprising weighting elements with l and 2steps respectively.

Upon addressing nodes H1 and N6, that is, after the departure nodes N1and arrival nodes N6 have been activated, the first of the signals Tldelivered by the output 20 of the clock 19 sets, or activates thearrival node N6. Then, the first of the signals T2 delivered by theoutput 18 of the clock 19 and following the above defined signals Tlmemorizes the link 5 alone since the link 10 is weighted 2.

At the second signal T1 the node N5 is memorized. At the second signalT2 it is only the link 10 which is memorized and links 4 and 8 will havetheir counters 35 stepped one unit. Then at a third signal T1, the nodeN8 is memorized and at a third signal T2, the link 13 is memorized aswell as link 4, while link 8 will have its counter 38 stepped by 2; andso on according to the rhythm of the signals T1 and T2.

At the fifth signal T1, the node N3 is memorized, and the memorizationofthe link 8 is inhibited.

Link 8, highly weighted represents, for joining the nodes N3 and N5, alonger passage than the passage constituted by the links 3 and 4; thus,link 8 will not be activated.

At the fifth T2 signal, the link 2 is memorized as well as link 9.

At the sixth signal T1, the nodes N2 and N7 are memorized. thispreventing the memorization of the link 6 and 7 issuing from the node N7and at a sixth signal T2, the loops 1 and 12 are memorized.

Finally, at the seventh signal T1, the nodes N1 and N9 are memorized,

At this moment, the departure node N1 being reached, the

signals T1 and T2 are blocked and a signal is sent to the input E1 ofthe departure nodal element and will instantaneously pass through thenoninverting amplifiers 27 of the nodal elements" constituting the nodesN1, N2, N3, N4, N5 and N6 and the AND gates 35 of the loop elementsconstituting the links 1,2,3,4 and 5. This signal will permit thedisplay of the itinerary constituted by the links 1 to 5 and shown inthick lines in FIG. 1 and it only, since, as the links 6,7,8 and 11 arenot memorized, .the AND'gates 35 associated with the loop elements"representing the links 6,7,8 and 11 are inhibited.

In this same figure, the loops 9 and 10 on the one hand and 12. 13 and10 on the other hand have been shown by thick lines. These linksconstitute two itineraries which do not reach the node Nl for thefollowing reasons: the itinerary of the links 9 and 10 does not reachthe node N1 due to the orientation of the link 6 whose memorization isprohibited by reason of the memorization of the original node N7, whilstthe path over links l2, l3 and 10 does not reach the node N1 due to thefact that the link 1 is memorized before the link 11 and thatconsequently the itineary of the links 11, 12, 13 and 10 is longer thanthe itinerary of the links 1 to 5.

Thus, only the shortest path permitting the passage from the node Nl tothe node N6 will be followed and may be displayed.

In certain cases there may exist between two nodes two lengthspresenting the same number of steps (one step corresponding to theemission of a signal T2) and that this number of steps is minimum. Thesetwo paths can either be between departure nodes and arrival nodes, orbetween intermediate nodes.

In such a case, the device displays the two equal lengths, or the doubleportion of the length. However, it is possible to eliminate, ifnecessary, one of the two lengths by giving preference to the other.

To this end, in these two lengths, the two loop elements" issuing fromthe same nodal element" and constituting the branching in question areconsidered and preference is given to one of the two loop elements" byconnecting the output S5 (FIG. 4) of the preferred loop elements to theinput 36 of the nonpreferred loop element so that its AND gate 35 isinhibited.

Moreover, one may at any moment temporarily or continuously eliminatecertain links from the network by applying an inhibiting signal to theinput 34 of the loop elements" in question.

Moreover, as indicated above, two nodes can be connected together by twolinks oriented in opposite direction possibly with two differentweightings.

The weighting of the links can also be modified by controlling theweighting elements.

The system not only enables problems of single point connections to besolved, but also general problems to be solved including a first familyof points. known as the departure family, and a second family of pointsknown as the arrival family, whatever may be the number of points ofthese families. lt is possible to select from a plurality of departurenodes and a single arrival node. the particular departure node which canconnect with the arrival node with the minimum number of steps, and toindicate the appropriate itinerary or itineraries. 7

Conversely. the system. assuming a single departure node and a pluralityof arrival nodes. permits those arrival nodes to be found which can bereached with the minimum number of steps and the appropriate itineraryor itineraries to be indicated.

Finally, assuming a plurality of departures nodes and a plurality ofarrival nodes, the system enables solving of the problem of the affinityof one assembly for another assembly" by plotting the departure node andarrival node" pairs separated by the minimum of steps and by indicatingthe appropriate itinerary or itineraries. In this case, as in the twopreceding cases, it is understood that the family of points in questioncan be reduced to one, so that the case then becomes analogous to thatof the example described above in connection with FIG. 1.

Such a system can be used in various fields of application, for examplethat of regulating urban traffic.

In this case, the problem is to guide the drivers on the road in a majorcenter towards their destinations starting from traffie centers. Thisguiding is effected according to the variable itineraries, determinedperiodically and taking into account at each instant, the state ofcongestion at the different arterial highways, the regulations in forceand unforeseeable elements such as accidents, roadworks etc. For each ofthese operations, a group of itineraries can be established between thetraffic centers in question. At the end of the signal cycle, theoptimized assembly of the guiding itineraries has been defined.

Each central traffic point or intersection of the network of streets isrepresented by a nodal element," Streets or parts of the streets joiningtwo adjacent intersections are represented by two parallel loop elementsof opposite direction in order possibly to represent the two possibledirections of traffic.

Weighting elements can be associated with each loop element" in order toconfer thereto a weighting ratio dependent upon the criteria adopted(kind of street possible obstacles, traffic lights, limited speed,possible congestion, etc.

A cyclic device successively sets up each central point as an arrivalpoint, all the other central points then being set up as departurepoints. All that remains is to inform the drivers of the optimizeditineraries by means of luminous or electromechanical signals placedbefore each crossroads and controlled from the terminal S4 of the loopelements.-

The system according to the invention may also be used for the purposeof increasing the speeds of certain public services, such as that offire engines for example, and also to optimize the problem ofevacuations in the case of emergency.

From among other possible applications, the calculation of the minimumpath itineraries in transoceanic flights, and the problem of dynamicprogrammation and the plotting of the critical paths are referred to.

Finally, such a system can constitute a subassembly Center ofInscription" (of which it only presents a simplified embodiment) of acomplex polyvalent memory as described in French Pat. No. 1,381,212ofthe 30th Sept. l96l,filed in the name of one of the inventors of thepresent application, and one of the functions of which is the plottingof the shortest sequence of intermediate actions between two situations.

The present invention is not limited to the described and shownembodiment but covers all relevant modifications thereto; the system maybe instrumented according to various technologies which could utilize,for example electronic, electromechanical, mechanical, hydraulic orpneumatic circuits, with elements having the same logic functions.

We claim:

1. Method of determining theshortest interconnection between a firstpoint, or set of points, to a second point. or set of points, saidpoints being located in a mesh network having interconnecting links,connecting said points together. comprising:

applying addressing signals to first and second points to identify andselect said first and second points within the points of the meshnetwork;

applying tracing signals emanating from said second addressed point toall interconnecting links connected thereto;

conducting said tracing signals from said links to all points connectedto said links, other than said second point, and, during said conductingstep;

timing the progression of said tracing signals through all said links inaccordance with predetermined characteristics of said links;

passing said tracing signals through said points connected to said linksand inhibiting said points, having said tracing signals passedtherethrough, from accepting tracing signals from other links connectedto respective points, at subsequent periods of time;

repetitively applying said tracing signals from said points tosubsequent links connected thereto;

inhibiting the first addressed point, first reached by a tracing signalfrom a connecting link, from accepting subsequent tracing signals fromother links connected thereto;

establishing through those points and links, through which a tracingsignal passed, a continuous closed connection, to establish a continuouscircuit between said first and second points; and

identifying those points and interconnecting links through which thetracing signal has passed and which are a part of said continuous,closed connection between said first and second points.

2. Method according to claim 1 wherein the step of timing theprogression of the tracing signal comprises the step of controlling thetiming of progression of said tracing signals in discrete timed steps,and controlling the number of steps required for passing of a signalthrough a link.

3. Method according to claim 1 further comprising the steps of:

generating control signals in those interconnecting links which are partof said continuous closed connection between said first and secondpoints; and

controlling the continuity of a second circuit path through those pointsand those interconnecting links, by said control signals.

4. System to trace the shortest path from a first point, or set ofpoints to a second point, or set of points, said points being locatedwithin a network of points, said network having interconnecting linksemanating from said points and interconnecting said points in apredetermined pattern, comprising:

a source of clock pulses (19);

a plurality of similar nodal circuit elements (FIG. 3) forming nodalpoints in the system, said nodal circuit elements having input andoutput terminals and means (26), controlled by said clock pulses and bysignals applied to at least one of said terminals, to establish acircuit path between said input and output terminals;

a plurality of similar link circuit elements (FIG. 4) forminginterconnecting links in the system, said link circuit elements beingconnected to said nodal circuit elements in accordance with the patternof the network, said link elements having input and output terminals andmeans, con trolled by said clock pulses and by signals applied to atleast one of said terminals, establishing a circuit path between saidinput and output terminals;

at least one time delay element (FIG. 5) selectively associated with,and connected to a link circuit element, said time delay element beingconnected to, and controlled by said source of clock pulses and havingmeans delaying signals passing through the circuit path of said linkelement by a preselected number of clock pulses. the number of pulses ofdelay being determined by'a characteristic of said delay element.whereby the output signals from the link elements having said time delayelement associated therewith will appear at a time delayed with respectto the clock pulses controlling said circuitpath; said circuit elementsadditionally comprising means (FIG.

3: 25-52; FIG. 4: E7-30-29) inhibiting establishment of a circuit paththrough a preceding link element connected to a nodal element when acircuit path has already been established from another link element tosaid nodal element;

means applying an addressing signal to one of said nodal circuitelements at a location in said network of points corresponding to saidsecond point, said addressing signal controlling said nodal circuitelement to enable application of said clock pulses to an outputterminal, and hence to any link circuit element connected thereto;

means applying an addressing signal to another one of said nodal circuitelements elements at another location in said network of points,corresponding to said first point, said second addressing signalinhibiting progression of a clock pulse applied to said second nodalelement from any link circuit element to a further connected linkcircuit element; and

whereby the circuit path requiring the least number of clock pulsesbetween said one nodal circuit element, and said other nodal circuitelement, over said link circuits, will be established between said oneand said other nodal circuit elements.

5. System according to claim 4 wherein said time delay (FIG. elementincludes a pulse counter (38) connected to have said clock pulsesapplied thereto, the delay time being a whole number of clock pulses.

6. System according to claim 4 wherein said circuit elements have a pairof parallel circuit paths, each path passing signals in oppositedirection.

7. System according to claim 4 wherein said nodal circuit elementscomprise a bistable memory and an AND gate (26), said AND gate (26)being controlled by a conjunction of timing signals from said clockpulse source (16) and said addressing signal, or by an output from alink circuit element being connected to said nodal circuit element; andinterconnecting means controlling change of state of said memory (25)upon appearance of an output from said AND gate.

8. System according to claim 7, including a second circuit in parallelwith said bistable memory (25) and said AND gate (26), said secondcircuit passing signals in a direction opposite to the signal pathsthrough said bistable memory.

9. System according to claim 7, wherein said link elements are oriented,each including a circuit comprising: a bistable memory (28), and an ANDgate (29) having an output connected to control said bistable memory;

an OR gate (16);

the output (S5) of said memory (28) and a first input (E6) of said ANDgate being respectively connected, through said OR gate (16) to an input(E2) of the AND gate (26) of the nodal element forming a connection tothe link element; and

said link element further including an inverter (30) connected to theoutput (S2) of the bistable memory (26) of the next nodal element, saidinverter having a further output connected to the AND gate (29) of thelink element.

10. System according to claim 9, wherein said time delay elementcomprises: a binary counter (38); and an AND gate (39) controlling saidcounter, one of the inputs (40) of said AND gate (39) is connected tothe output S3) of the bistable memory (25) of the nodal element inadvance of the link element with which the time delay element isassociated;

a decoding circuit (42);

the output of the counter (38) being applied to said decoding circuit,said decoding circuit being preset to provide an output pulse only aftera predetermined number of input pulses from said counter have beencounted to define said characteristic of the delay element; and

the output. after decoding, being applied to an additional input (31.32) to the AND gate 29 of the link element to which the delay element isconnected.

11. System according to claim 9. wherein said link element is orientedand comprises an inhibiting circuit (34) including an amplifier (33).the output of said amplifier being connected to an additional input ofthe AND gate (29) of the link element.

12. System according to claim 4, wherein said source of clock pulsessupplied a pair of pulse output signals (T1, T2), one of which (T7) isconnected (20-E3) to control the nodal elements (FIG. 3) and the other(T2) is connected (l8E5) to control the link elements (FIG. 4).

13. System according to claim 9, wherein: said circuit path establishinga selected itinerary between departure and arrival nodes includes anamplifier (27) associated with each of the nodal elements;

an OR gate 17);

an AND gate (35) associated with each of said link elements, the outputof said AND gate (35) being connected (S4) through said OR gate (17) tothe input of the amplifier (27) associated with the nodal element nextconnected to the link element;

said AND gate (35) having additional inputs connected to the output ofthe bistable memory (28) of the link element.

14. System according to claim 12, including: an additional AND gate (35)included in said circuit path; an inhibiting amplifier (37);

said additional AND gate (35) being controlled by said inhibitingamplifier (37); and

means (36) controlling the operation of said inhibiting amplifier toinhibit progression of signals in said path.

15. System according to claim 4, wherein: the circuit path establishingthe selected itinerary, or itineraries, between departure and arrivalnodes includes a circuit (FIG. 6) associated with each of said nodalelements and successively comprising a first AND gate (50) with twoinputs;

a first bistable trigger circuit (53);

a second AND gate (56) with two inputs;

a second bistable trigger circuit (57); and

one of the inputs of said first and the second AND gates being connectedto receive, at one of the their inputs (52, 55), each successively orsimultaneously, an activation signal (U U respectively and an otherinput of said first and second AND gates being connected in said circuitpath to control propagation of a signal along said path.

16. System according to claim 4 wherein said nodal circuit elements(FIG. 3) and said link circuit elements (FIG. 4) each includes acontrollable bistable circuit (25, 28) and a conjunctive logic circuit(26, 29) controlling the state of said bistable circuit in therespective circuit element, one of the inputs of the conjunctive logiccircuit being connected to said clock pulse source and the other inputbeing connected to the out put from a connected circuit element and tosaid means applying an addressing signal.

a 17. System according to claim 16 wherein each said link elements has atime delay element (FIG. 5) associated therewith, said time delayelement including a settable pulse counter (38-43) connected to saidclock pulse source (19) and delaying transmission of pulses by said linkelements under control of the count setting of the pulse counter.

18. System according to claim 16 wherein each said circuit element has apair of independent, parallel circuit paths, passing signals in oppositedirection; and one of said independent circuit paths in the link circuit(FIG. 4) includes a control element (35) closing said independentcircuit path under control of the state of said bistable circuit (28).

1. Method of determining the shortest interconnection between a firstpoint, or set of points, to a second point, or set of points, saidpoints being located in a mesh network having interconnecting links,connecting said points together, comprising: applying addressing signalsto first and second points to identify and select said first and secondpoints within the points of the mesh network; applying tracing signalsemanating from said second addressed point to all interconnecting linksconnected thereto; conducting said tracing signals from said links toall points connected to said links, other than said second point, and,during said conducting step; timing the progression of said tracingsignals through all said links in accordance with predeterminedcharacteristics of said links; passing said tracing signals through saidpoints connected to said links and inhibiting said points, having saidtracing signals passed therethrough, from accepting tracing signals fromother links connected to respective points, at subsequent periods oftime; repetitively applying said tracing signals from said points tosubsequent links connected thereto; inhibiting the first addressedpoint, first reached by a tracing signal from a connecting link, fromaccepting subsequent tracing signals from other links connected thereto;establishing through those points and links, through which a tracingsignal passed, a continuous closed connection, to establish a continuouscircuit between said first and second points; and identifying thosepoints and interconnecting links through which the tracing signal haspassed and which are a part of said continuous, closed connectionbetween said first and second points.
 2. Method according to claim 1wherein the step of timing the progression of the tracing signalcomprises the step of controlling the timing of progression of saidtracing signals in discrete timed steps, and controlling the number ofsteps required for passing of a signal through a link.
 3. Methodaccording to claim 1 further comprising the steps of: generating controlsignals in those interconnecting links which are part of said continuousclosed connection between said first and second points; and controllingthe continuity of a second circuit path through those points and thoseinterconnecting links, by said control signals.
 4. System to trace theshortest path from a first point, or set of points to a second point, orset of points, said points being located within a network of points,said network having interconnecting links emanating from said points andinterconnecting said points in a predetermined pattern, comprising: asource of clock pulses (19); a plurality of similar nodal circuitelements (FIG. 3) forming nodal points in the system, said nodal circuitelements having input and output terminals and means (26), controlled bysaid clock pulses and by signals applied to at least one of saidterminals, to establish a circuit path between said input and outputterminals; a plurality of similar link circuit elements (FIG. 4) forminginterconnecting links in the system, said link circuit elements beingconnected to said nodal circuit elements in accordance with the patternof the network, said link elements having input and output terminals andmeans, controlled by said clock pulses and by signals applied to atleast one of said terminals, establishing a circuit path between saidinput and output terminals; at least one time delay element (FIG. 5)selectively associated with, and connected to a link circuit element,said time delay element being connected to, and controlled by saidsource of clock pulses and having means delaying signals passing throughthe circuit path of said link element by a preselected number of clockpulses, the number of pulses of delay being determined by acharacteristic of said delay element, whereby the output signals fromthe link elements having said time delay element associated therewithwill appear at a time delayed with respect to the clock pulsescontrolling said circuit path; said circuit elements additionallycomprising means (FIG. 3: 25-S2; FIG. 4: E7- 30- 29) inhibitingestablishment of a circuit pAth through a preceding link elementconnected to a nodal element when a circuit path has already beenestablished from another link element to said nodal element; meansapplying an addressing signal to one of said nodal circuit elements at alocation in said network of points corresponding to said second point,said addressing signal controlling said nodal circuit element to enableapplication of said clock pulses to an output terminal, and hence to anylink circuit element connected thereto; means applying a an addressingsignal to another one of said nodal circuit elements elements at anotherlocation in said network of points, corresponding to said first point,said second addressing signal inhibiting progression of a clock pulseapplied to said second nodal element from any link circuit element to afurther connected link circuit element; and whereby the circuit pathrequiring the least number of clock pulses between said one nodalcircuit element, and said other nodal circuit element, over said linkcircuits, will be established between said one and said other nodalcircuit elements.
 5. System according to claim 4 wherein said time delay(FIG. 5) element includes a pulse counter (38) connected to have saidclock pulses applied thereto, the delay time being a whole number ofclock pulses.
 6. System according to claim 4 wherein said circuitelements have a pair of parallel circuit paths, each path passingsignals in opposite direction.
 7. System according to claim 4 whereinsaid nodal circuit elements comprise a bistable memory (25) and an ANDgate (26), said AND gate (26) being controlled by a conjunction oftiming signals from said clock pulse source (16) and said addressingsignal, or by an output from a link circuit element being connected tosaid nodal circuit element; and interconnecting means controlling changeof state of said memory (25) upon appearance of an output from said ANDgate.
 8. System according to claim 7, including a second circuit inparallel with said bistable memory (25) and said AND gate (26), saidsecond circuit passing signals in a direction opposite to the signalpaths through said bistable memory.
 9. System according to claim 7,wherein said link elements are oriented, each including a circuitcomprising: a bistable memory (28), and an AND gate (29) having anoutput connected to control said bistable memory; an OR gate (16); theoutput (S5) of said memory (28) and a first input (E6) of said AND gatebeing respectively connected, through said OR gate (16) to an input (E2)of the AND gate (26) of the nodal element forming a connection to thelink element; and said link element further including an inverter (30)connected to the output (S2) of the bistable memory (26) of the nextnodal element, said inverter having a further output connected to theAND gate (29) of the link element.
 10. System according to claim 9,wherein said time delay element comprises: a binary counter (38); and anAND gate (39) controlling said counter, one of the inputs (40) of saidAND gate (39) is connected to the output (S3) of the bistable memory(25) of the nodal element in advance of the link element with which thetime delay element is associated; a decoding circuit (42); the output ofthe counter (38) being applied to said decoding circuit, said decodingcircuit being preset to provide an output pulse only after apredetermined number of input pulses from said counter have been countedto define said characteristic of the delay element; and the output,after decoding, being applied to an additional input (31, 32) to the ANDgate 29 of the link element to which the delay element is connected. 11.System according to claim 9, wherein said link element is oriented andcomprises an inhibiting circuit (34) including an amplifier (33), theoutput of said amplifier being connected to an additional input of theAND gate (29) of the link element.
 12. System according to cLaim 4,wherein said source of clock pulses supplied a pair of pulse outputsignals (T1, T2), one of which (T7) is connected (20- E3) to control thenodal elements (FIG. 3) and the other (T2) is connected (18- E5) tocontrol the link elements (FIG. 4).
 13. System according to claim 9,wherein: said circuit path establishing a selected itinerary betweendeparture and arrival nodes includes an amplifier (27) ad associatedwith each of the nodal elements; an OR gate (17); an AND gate (35)associated with each of said link elements, the output of said AND gate(35) being connected (S4) through said OR gate (17) to the input of theamplifier (27) associated with the nodal element next connected to thelink element; said AND gate (35) having additional inputs connected tothe output of the bistable memory (28) of the link element.
 14. Systemaccording to claim 12, including: an additional AND gate (35) includedin said circuit path; an inhibiting amplifier (37); said additional ANDgate (35) being controlled by said inhibiting amplifier (37); and means(36) controlling the operation of said inhibiting amplifier to inhibitprogression of signals in said path.
 15. System according to claim 4,wherein: the circuit path establishing the selected itinerary, oritineraries, between departure and arrival nodes includes a circuit(FIG. 6) associated with each of said nodal elements and successivelycomprising a first AND gate (50) with two inputs; a first bistabletrigger circuit (53); a second AND gate (56) with two inputs; a secondbistable trigger circuit (57); and one of the inputs of said first andthe second AND gates being connected to receive, at one of the theirinputs (52, 55), each successively or simultaneously, an activationsignal (U1, U2) respectively and another input of said first and secondAND gates being connected in said circuit path to control propagation ofa signal along said path.
 16. System according to claim 4 wherein saidnodal circuit elements (FIG. 3) and said link circuit elements (FIG. 4)each includes a controllable bistable circuit (25, 28) and a conjunctivelogic circuit (26, 29) controlling the state of said bistable circuit inthe respective circuit element, one of the inputs of the conjunctivelogic circuit being connected to said clock pulse source and the otherinput being connected to the output from a connected circuit element andto said means applying an addressing signal.
 17. System according toclaim 16 wherein each said link elements has a time delay element (FIG.5) associated therewith, said time delay element including a settablepulse counter (38- 43) connected to said clock pulse source (19) anddelaying transmission of pulses by said link elements under control ofthe count setting of the pulse counter.
 18. System according to claim 16wherein each said circuit element has a pair of independent, parallelcircuit paths, passing signals in opposite direction; and one of saidindependent circuit paths in the link circuit (FIG. 4) includes acontrol element (35) closing said independent circuit path under controlof the state of said bistable circuit (28).